The present invention relates to a semiconductor device circuit for a delay locked loop (DLL); and more particularly, to a register controlled DLL.
Generally, a clock is used as a reference for adjusting operation timing. Furthermore, the clock may be used for guaranteeing a rapid operation without any error.
When an external clock is internally used in a circuit as an internal clock, a clock skew is generated by data paths and function blocks in the circuit. To have a same phase of the internal clock as that of the external clock, a delay locked loop (DLL) is used.
Recently, the DLL is much more commonly used for a synchronous semiconductor memory as well as a double data rate synchronous dynamic random access memory (DDR SDRAM) than a phase locked loop (PLL) because the DLL is less affected by a noise than the PLL. Especially, among many kinds of DLLs, a register controlled DLL is most commonly used.
For the synchronous semiconductor memory, a negative delay is reflected to make data output synchronized with the external clock, wherein the negative delay is generally obtained by compensating a delay element of a clock path or a data path after receiving the external clock.
FIG. 1 is a block diagram illustrating a conventional register controlled DLL for the DDR SDRAM. The register controlled DLL uses the internal clocks (Rclk and Fclk) outputted from a first and a second clock input buffer 100 and 102. The first clock input buffer 100 generates the internal clock (Rclk) synchronized at a rising edge of an ordinary external clock (CLK) by buffering the ordinary external clock (CLK). In addition, the second clock input buffer 102 generates the internal clock (Fclk) synchronized at a rising edge of a sub ordinary external clock (/CLK) by buffering a sub ordinary external clock (/CLK).
Referring to FIG. 1, the register controlled DLL includes the followings: a clock divider 110 generating a divided clock (Fb_D8) by dividing the internal clock (Rclk) by X, wherein X=8, wherein X is a positive integer; a first delay chain 120 inputting the internal clock (Rclk); a second delay chain 122 inputting the internal clock (Fclk); a third delay chain 124 inputting a clock (Fb_D8) divided for a phase comparison; a shift register 160 deciding a delay amount of the first, second and third delay chains 120, 122 and 124; a delay model 130 reflecting the delay element of a real clock path and a data path by inputting an output (Fb_DC) of the third delay chain 124; a phase comparator 140 for comparing the phase of the divided clock (Fb_D8) with the output (Fb_DM) of the delay model 130; a first DLL driver 170 for generating a DLL clock (Rclk_DLL) through getting a permission for the output (Rclk_DC) of the first delay chain during a delay locking; a second DLL driver 172 for generating another DLL clock (Fclk_DLL) through getting another permission for the output (Fclk_DC) of the second delay chain 122 during the delay locking; and a shift register controller 150 for controlling a shift direction of the shift register 160 by inputting the output (CS_PC) of the phase comparator 140.
FIG. 2 is a circuit diagram showing the delay chain of the register controlled DLL in accordance with the prior art. All of the first, second and third chains 120, 122 and 124 have a same constitution as shown in FIG. 2.
Referring to FIG. 2, m*n NAND gate respectively taking the input clock (clk_in) and each of delay selective signals expressed in an order of sel_1, . . . , sel_mxe2x88x921, sel_m, sel_m+1, . . . , and sel_m*n as one input and another input is formed. In addition, m*n delay units expressed in an order of DU1, . . . , DUmxe2x88x921, DUm, DUm+1, . . . , DUm*n is formed, wherein the delay units are controlled by each NAND gate.
Herein, each delay unit is constituted with two NAND gates, and especially, the Mth delay unit (DUm) is constituted with a first NAND gate taking the output of a former delay unit (DUmxe2x88x921) as one input and taking the output of the NAND gate (NANDm) corresponding to the delay unit (DUm) as another input, and a second NAND gate (NAND101) taking a supply power (VDD) as one input and taking the output of the first NAND gate (NAND100) as another input. Herein, the supply power is taken as the input for the first delay unit (DU1) instead of a previous delay unit because the first delay unit (DU1) doesn""t have any former delay unit.
FIG. 3 is a circuit diagram showing a shift register of the register controlled DLL in accordance with the prior art.
Referring to FIG. 3, the shift register is constituted with many m*n stages. Describing one stage, each stage is constituted with a reverse latch (L) constituted with the NAND gate and an inverter (INV), a switching unit (S) for changing a value latched to the latch by being controlled by a shift signal such as sre, sro, slo and sle, and a logic composition unit (C) for compositing an ordinary output of the latch of a former stage and sub ordinary output of the latch of a next stage.
Herein, the latch of each stage accepts a reset signal (resetz) as one input of the NAND gate for an initialization and the sub ordinary output of the corresponding latch (L) is taken as another input.
The switching unit (S) is connected to an ordinary output terminal of the latch (L). In addition, the switching unit (S) is constituted with a first NMOS transistor M1 controlled by an odd shift right signal (sro), a second NMOS transistor M2 connected to the sub ordinary output terminal of the latch (L) and controlled by an even shift left signal (sle), a third NMOS transistor M3 for selectively generating a path between a ground power and the ordinary output terminal of the latch (L) together with the first NMOS transistor M1 by being controlled by the sub ordinary output of the latch of the former stage, and a fourth NMOS transistor M4 for selectively generating another path between the ground power and the sub ordinary output terminal of the latch (L) together with the second NMOS transistor M2 by being controlled by the ordinary output of the latch of the next stage. In addition, the former stage and the next stage are controlled by the even shift right signal (sre) and the odd shift left signal (slo) among the shift signals, e.i., sre, sro, slo and sle.
Furthermore, the logic composition unit (C) is embodied by using an OR gate inputting the sub ordinary output of the ordinary output terminal of the latch of the former stage and the sub ordinary output of the latch of the next stage.
FIG. 4 is a timing diagram showing the register controlled DLL illustrated in FIG. 1.
The operation of the register controlled DLL in accordance with the prior art will be explained referring to FIGS. 1 to 4.
First, the clock divider 110 generates a clock Fb-D8, which is synchronized in every 8th clock of the ordinary and sub ordinary clocks by dividing the internal clock (Rclk) by 8. As a matter of convenience, the divided output (Fb_D8) of the clock divider is not shown in FIG. 4.
During an initial operation, the output (Fb_D8) of the clock divider 110 is inputted into the first delay unit of the third delay chain 124 and passes through the third delay chain 124. Thereafter, the output (Fb_08) passes through the delay model 130, and consequently, a required delay amount is obtained and the final output (Fb_08) of the clock divider 110 is output.
The phase comparator 140 compares the divided clock (Fb_D8) with the rising edge of the output clock (Fb_DM) of the delay model 130. The shift register controller 150 outputs a shift control signal (CS_SM2SR) in accordance with the output (CS_PC) of the phase comparator 140. For a delay monitoring, the clock (Fb_D8) inputted into the third delay chain 124 may be used as a standard clock. However, the divided clock (Fb_08) is not used for the standard clock. Usually, the divided clock (Fb_08) is reversed, and thereafter used as the standard clock.
In addition, the shift register 160 outputs the delay selective signal (CS_SR) by carrying out a shift operation corresponding to the shift control signal (CS_SM2SR), and thereby deciding the delay amount of the first, second and third delay chain 120, 122 and 124 by enabling one of delay units constituting the first, second and third delay chain 120, 122 and 124.
Thereafter, the delay locking is completed at the moment that a minimum jitter is obtained between the output clock (Fb_DM) of the delay model 130 of which the delay amount has been controlled and the divided clock (Fb_D8) by comparing the two clocks each other. At this time, the DLL clocks (Rclk_DLL and Fclk_DLL) outputted from the first and second DLL driver 170 and 172 can control an output buffer for allowing output data to be synchronized with the ordinary external clock (CLK) and the sub ordinary external clock (/CLK) and outputted.
As mentioned, in case that the number of the delay units constituting the first, second and third delay chain 120, 122 and 124 is m*n, the number of the latches included in the shift register 160 should be m*n too.
In case that the register controlled DLL in accordance with the prior art described above is set to perform a shifting operation from the left of the shift register 160, i.e., a shift right, during the initial operation, maximum number, that is, m*n clock cycles are required for the delay locking. In FIG. 4, a case requiring a delay locking time of a total 98 clock cycles is exemplified. Also, a case that the register controlled DLL is set up to perform the shift operation from the right of the shift register, i.e., a shift left, during the initial operation, the maximum number, that is, m*n clock cycles are required for the delay locking too.
Furthermore, the number of the delay units should be increased in order that the register controlled DLL is operated in a range of much broader operation frequency. The other hand, the range of the operation frequency is decreased, in case of reducing the delay time of the delay unit for the purpose of reducing the jitter. Consequently, the number of the delay units should be increased to satisfy both of an operation frequency property and a jitter property. However, if the number of the delay units is increased, a chip area should be increased. In short, the operation frequency property and jitter property of the conventional register controlled DLL have a relation of an inverse proportion.
It is, therefore, an object of the present invention to provide a register controlled delay locked loop (DLL) capable of having much faster delay locking time and satisfying an operation frequency property and a jitter property together with minimizing a chip area.
In accordance with an aspect of the present invention, there is provided a register controlled delay locked loop (DLL) using an internal clock synchronized with an external clock as a delay monitoring clock and a comparison reference clock, the register controlled delay locked loop (DLL) including: a first delay line having a plurality of sub delay chains grouped with a plurality of delay units for receiving the internal clock; a second delay line having a plurality of sub delay chains grouped with a plurality of delay units and receiving the delay monitoring clock and generating a second delayed clock; a delay model for generating a delay model signal by reflecting a delay condition of a real clock path on the second delayed clock from the second delay line; a phase comparison unit for generating a phase comparison signal by comparing a phase of the comparison reference clock with the delay model signal from the delay model; a shift register control unit for generating a shift control signal by responding to the phase comparison signal from the phase comparison unit; a master shift register for selecting one of the sub delay chains of the first delay line and the second delay line by responding to the shift control signal; and a slave shift register for selecting one of the delay units in the sub delay chain selected by the master shift register by responding to the shift control signal.
In accordance with an aspect of the present invention, there is provided a register controlled delay locked loop (DLL) using an internal clock synchronized with an external clock as a delay monitoring clock source and a comparison standard clock source, including: a first delay line having a plurality of sub delay chains grouped with a plurality of slave delay units and one master delay unit for receiving the internal clock and generating a first delay signal; a second delay line having a plurality of sub delay chains grouped with a plurality of slave delay units and one master delay unit for receiving the delay monitoring clock as the input and generating a second delay signal; a delay model for generating a delay model signal by reflecting a delay condition of a real clock path on the second delayed signal from the second delay line; a phase comparison unit for comparing a phase of the comparison reference clock with the delay model signal from the delay model and generating a phase comparison signal; a shift register control unit for generating a shift control signal by responding to the phase comparison signal from the phase comparison unit; a master shift register for selecting one among the master delay units of the first delay line and the second delay line by responding to the shift control signal; and a slave shift register for selecting one of the slave delay units in the sub delay chain selected by the master shift register by responding to the shift control signal.